A FO-WLP includes a molded package body in which one or more microelectronic devices are embedded. The embedded microelectronic devices typically include at least one semiconductor die, but can also include other devices, such as Surface Mount Devices or “SMDs.” The microelectronic devices are typically embedded in the molded package body at a location substantially coplanar with the frontside of the package body. One or more frontside Redistribution Layers (RDLs) containing electrically-conductive interconnect lines are build-up over the frontside of the package body to provide the desired interconnections between the packaged devices (if multiple devices are embedded in the FO-WLP) and an externally-accessible contact array formed over the frontside RDLs. In instances wherein the FO-WLP has a double-sided package architecture, additional RDLs can also be produced over the backside of the molded package body. Backside RDLs are usefully produced when, for example, the FO-WLP further includes one or more Backside Contacts (BSCs), which extend to the backsides of the packaged devices to provide electrical connection thereto. Microelectronic devices requiring backside interconnection can include certain types of Field Effect Transistors (FETs), Silicon Controlled Rectifiers (SCRs), Resonant Gate Transistors (RGTs), Insulated Gate Bipolar Transistors (IGBT), and other active and passive devices.
The above-described double-sided package architecture usefully provides interconnection to the backsides of one or more microelectronic devices embedded within a molded package body. Additionally, as the BSCs are typically formed by dispensing bodies of an Electrically Conductive Adhesive (ECA) over the packaged devices, variances in device height can readily be accommodated through adjustments in BSC thickness. These advantages notwithstanding, double-sided package architectures remain limited in certain respects. As a primary limitation, the build-up of backside RDLs can add considerable time, cost, and complexity to the FO-WLP manufacturing process. Additionally, such package architectures are often produced to include Through Package Vias (TPVs) to provide electrical interconnection between the frontside and backside RDLs, which further adds cost and complexity to the FO-WLP manufacturing process.
It is thus desirable to provide FO-WLPs wherein backside interconnection to packaged devices is provided in a relatively straightforward and structurally robust manner and, preferably, without reliance upon backside RDLs, TPVs, and other such structures associated with conventional double-sided package architectures. It would also be desirable if, in at least some embodiments, such backside interconnection could be provided to multiple microelectronic devices having varying heights contained within a single FO-WLP. Finally, it would be desirable to provide methods for fabricating FO-WLPs having the foregoing characteristics on a relatively high volume, low cost basis. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Background.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.